As technology advances, a need arises for digital circuitry capable of processing data at high data rates, e.g., in excess of a few hundred Megabits per second. At these data rates, integrated circuits fabricated of high-speed semiconductor materials have a maximum gate count significantly lower than that of more conventional technologies. That is, a high-speed chip may contain hundreds of gates, whereas a conventional silicon chip may contain hundreds of thousands of gates.
The number of gates, or more precisely the chip area, used by a given digital circuit on a high-speed substrate is therefore of significant importance to the designer. Assuming a specific number of gates per chip, the fewer the number of gates required per circuit, the greater the number of circuits per chip. This in turn effects a decrease in the number of chips required of a given device and decreases the overall production cost of that device.
Additionally, power consumption is often a limiting design factor. Satellites, portable telephones, and other communications devices, for example, may be powered by solar cells, batteries, or other limited power sources. Any reduction in circuit power consumption is therefore a prime consideration in the design of such devices. For a given technology at a given data rate, a single gate requires a specific amount of power. Therefore, the fewer the number of gates required for a given circuit, the less power that circuit requires, and the more efficient the circuit becomes. When this effect is multiplied by the number of circuits required of a typical device, the savings in power, hence the increase in efficiency, may be considerable.
When the constraints of power are coupled with high data rates, the problem is exacerbated. For a given gate in a given technology, a decrease in data rate often brings about a corresponding decrease in power consumption. Therefore, the fewer gates in a given circuit operating at a high data rate the lower the circuit power consumption, the lower the chip power consumption, and the lower the device power consumption.
Power consumption equates with heat. The less power consumed by a device, the less heat generated and the less heat that must be dissipated. On the chip level, a reduction in chip power consumption results in a decrease in chip temperature and an increase in chip longevity. This can be a critical factor in the design of devices, such as satellites, where the replacement of prematurely failed chips is impractical.
Normally, the lower the data rate of a given circuit, the easier it is to implement. High data rate circuits often require more precise and more exotic techniques of design and implementation. Since the trend is toward higher and higher data rates, there is an ongoing increase in design exoticism, with a correspondingly increasing design cost. It is of benefit to the designer, therefore, to minimize the number of gates per chip dedicated to processing data at high data rates.
FIG. 1 depicts a prior-art eight-bit temporal-to-spacial converter 10 containing a twisted-ring (Johnson) counter 11. In the embodiment of FIG. 1, counter 11 is a sequencer made up of n/2 clocked D-type flip-flops 12, where N is the number of states of counter 11, i.e., the number of bits of converter 10. Each flip-flop 12 is clocked by a clock signal 13. Therefore, each flip-flop 12 in counter 11 operates at the rate of clock signal 13 (rate S).
Converter 10 also contains a shift register 14 made up of N clocked d-type flip-flops 12 configured to convert a serial input signal 15 into a parallel output signal 16. Each flip-flop 12 of shift register 14 is also clocked by clock signal 13. Therefore, each flip-flop 12 in shift register 14 also operates at rate S.
Additionally, converter 10 contains a transfer register 17 also made up of clocked D-type flip-flops 12. Flip-flops 12 in transfer register 17, however, are clocked by a transfer signal 18 generated by counter 11. Since counter 11 has N states, i.e., requires N cycles of clock signal 13 per cycle of counter 11, flip-flops 12 of transfer register 17 need only operate at rate S/N.
Since, as is well known in the art, each flip-flop 12 is made up of two latches (not shown), with each latch being made up of two to four gates (not shown), the conventional embodiment of converter 10, as depicted in FIG. 1, contains twenty-four latches (forty-eight to ninety-six gates) encompassed in counter 11 and shift register 14, all of which operate at rate S. Assuming high-speed operation, e.g., in the multi-gigabit per second range, converter 10 represents a significant combination of the problems discussed above. Therefore, any reduction in gate count and/or gate rate is highly desirable.
It is an advantage of the present invention, therefore, that the power consumption and related heat dissipation of a given device are reduced. This is effected in one form by significantly reducing the number of gates per circuit for circuits involving sequencers. This is effected in another form by reducing the number of those gates requiring the full high-speed data rates and the design exoticism associated therewith.
It is also an advantage of the present invention that the performance of high-data-rate circuits involving sequencers is improved. This is effected in one form by reducing the loading of certain signal lines in circuits involving sequencers.
It is another advantage of the present invention that the production and design costs of a given device are reduced. This is effected in one form by significantly reducing the number of gates per circuit for circuits involving sequencers, thus increasing the number of circuits per chip and reducing the number of chips per device. This is effected in another form by reducing the number of those gates requiring the full high-speed data rates and the design exoticism associated therewith.